4/5/2024 0 Comments Ti connect 1.6.1 macintoshAdded 35-bit Hamming Matrix figure to "Error Checking and Correction Algorithm" section.Added 136-bit Hamming Matrix figure to "Error Checking and Correction Algorithm" section.Added "ECC Bits Required Based on Data Width" table to "Error Checking and Correction Algorithm" section.Error Checking and Correction Controller Revision History Date Added parity error handling information to the "L1 Caches" section and the "Cache Controller Configuration" topic of the "L2 Cache" section.Added the "Configuration for ACP Use" subsection to the "Accelerator Coherency Port" section.Added the "Shared Requests on ACP" subsection to the "Accelerator Coherency Port" section.Added the "AxUSER and AxCACHE" subsection to the "Accelerator Coherency Port" section.Added bus transaction scenarios in the "Accelerator Coherency Port" section.Added address maps for the Cortex*-A9 MPU subsystem and the L2 cache controller.Corrected allowed AxID values in "Accelerator Coherency Port" section.Added "L2 Cache Parity" subsection in "L2 Cache" section. ![]() Renamed "ECC Support" L2 subsection to be "Single Event Upset Protection".Added "Configuring AxCACHE Sideband Signals" and "Configuring AxUser Sideband Signals" subsections to the " AXI* Master configuration for ACP Access" section.Configuring AxPROT Sideband Signals for Coherent AccessesĪdded information about maintaining cache coherency in the Accelerator Coherency PortĪdded details about arbitration behavior in the SCU when the ACP is not being used in the Implementation Details of the Snoop Control Unit section,.Clarified block diagram of SDRAM 元 interconnectĪdded note regarding Cortex* -A9 output flags.Īdded clarification for ACP usage requirements by adding the following chapters:.Added information about quality of service.Added register details for address remapping.Added information about the observation network.Added information about the SDRAM scheduler.Added address maps and register definitions.Clarify power domains in "Functional Description of the SDRAM 元 Interconnect".Correct size of HPS-to-FPGA region in "MPU Address Space"."Sharing I/O between the EMIF and the FPGA": New section, discusses constraints on sharing I/Os with EMIF."Configuring SDRAM Burst Sizes": Refers to guidelines for selecting burst sizes."Controlling Quality of Service from Software": Added note about register access."System Interconnect Slave Interfaces" table: Corrected acceptance values for Lightweight HPS-to-FPGA Bridge and Lightweight HPS-to-FPGA Bridge.Remove io48_hmc_mmr Address map and registers from System Interconnect Address Map and Register Definitions section.Remove Hard Memory Controller Memory Mapped Registers section.Remove 32-bit bus from 元 interconnect to hard memory controller in the SDRAM 元 Interconnect Block Diagram and System Integration section. ![]() Clarify relationship between quality of service (QoS) and arbitration.Updated ddrConf bitfield description in the ddr_T_main_Scheduler_Ddrconf register to include encodings. Updated Arria 10 HPS Available Address Maps to explain how to access the registers that are connected to the HPS-to-FPGA AXI* Master Bridge. Added information regarding CSEL programming in the "Clock Configuration" section.Added "MPU" and "JTAG" sub-sections to the "Secure Debug" section.Added summary of "Security State" and "Security Check" and "Secure Serial Interface" features. ![]()
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